/**
 ** 模拟数据输入的数据生成器
**/
module dataGenerator (
    input wire clk,
    input wire rst,
    input wire write_arbition,            //写仲裁结果信号
    input wire [9:0] seed,
    output reg data_ready,
    output reg [31:0] data,               //数据
    output reg [5:0] data_priority,
    output reg [5:0] data_target_port,
    output reg [9:0] data_wait_time,
    output reg data_write_en,
    output reg [9:0] data_size
);
    reg [9:0] temp_size;
    reg [1:0] work_state; //工作状态
    reg [5:0] temp_port;
    integer dataSeed;
    reg flag;

    //工作状态的转移逻辑
    always @(posedge clk) begin
        if (rst) begin
            //复位信号
            flag = 0;
            work_state = 2'b00;
            dataSeed = seed;
        
            if (flag==0 && dataSeed>0) begin
                data_size <= 64 + {$random(dataSeed)} % 65;
                data_target_port <= {$random(dataSeed)} % 4;
                data_write_en <= 1;
                data_priority <= {$random(dataSeed)} % 8;
                data_wait_time <= 1;
                flag <= 1;
                data_ready <= 0;
            end
        end
        else begin
            if (write_arbition && work_state == 2'b00) begin
                work_state <= 2'b01;
                data_write_en <= 0;
                //开始传输数据，将优先级降低到最低
                data_priority <= 0;
                temp_size <= data_size;
            end

            if (work_state == 2'b01) begin
                if (temp_size == 1) begin
                    //最后一个字的数据发送完毕，修改工作状态为空闲，可以处理其他内容
                    work_state <= 2'b00;
                    data_ready <= 1'b0;
                    temp_size <= 64 + {$random(dataSeed)} % 65;
                    data_size <= 64 + {$random(dataSeed)} % 65;
                    data_target_port <= {$random(dataSeed)} % 4;
                    data_write_en <= 1;
                    data_priority <= {$random(dataSeed)} % 8;
                    data_wait_time <= 1;
                end
                else begin
                    //继续发送数据
                    data_ready <= 1'b1;
                    data <= 64 + {$random(dataSeed)} % 449;
                end

                temp_size <= temp_size - 1;
            end
        end
    end
endmodule